In DC-DC power supplies, the co-packaging of both the control and synchronous MOSFET (metal-oxide semiconductor field-effect transistor) devices in a single package has better area efficiency and is currently the trend within the industry. FIGS. 1, 2, and 3 illustrate different examples of these types of die packages that are available within the market. Specifically, FIG. 1 is an isometric view of a conventional PPAIR package 100 that includes two dies together with wire bonding. The wire bonding is illustrated by a magnified view 102. In addition, FIG. 2 illustrates top and bottom views of a conventional PPAIR package 200 that includes two dies together with clip bonding. The clip bonding is illustrated by a magnified view 202. Furthermore, FIG. 3 is an isometric view of a conventional stack die package 300 that includes two stacked dies along with clips. It is pointed out that there are disadvantages associated with these conventional die packages.
For example, for a PPAIR package (e.g., 100 or 200), the LS (low side) die and the HS (high side) die are situated near each other on the same surface. As such, for a given fixed package size, the die size within the PPAIR package will be limited and therefore the drain-to-source resistance (Rds) and current handling capability will be affected. It is pointed out that for a stack die package (e.g., 300), the die size can be larger. However, due to the soldering process of the clips, it can contaminate the wire bond pad surfaces on the die and lead post. Consequently, there is a concern about the assembly yield and the reliability of the bonded wires of stack die packages. Furthermore, the wire bonding process of a stack die package can require silver plating on the lead frame which adversely increases the lead frame cost.